Experience: 2-10 years
Job Description:
• Hands on experience of coding in Verilog and VHDL.
• Understanding of Power Intent, Power estimation and checks.
• Experience of Design rule checks and Clock domain crossing checks using Spyglass or similar tool.
• Specification writing.
• IP RTL development experience.
• Good knowledge of version control tools like Clearcase and Design sync.

Experience: 3-15 years
Job Description:
• Expert in UVM/OVM for Verification
• System verilog assertions
• Perl
• Functional + Code Coverage
• Verilog and VHDL
• Tools like Synopsys VCS,Cadence IUS or Mentor Questasim is Preferable
• Image Sensor knowledge is a plus
• Experience with SPI,AHB,AXI,PCIe,DDR is a plus

Experience: 2-10 years
Job Description:
• Thorough understanding and knowledge of the entire Back end flow rtl to gdsii
• Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus
• Should have expertise in Timing analysis and closure
• Should have Tcl and perl scripting skills
• Should have work experience in the latest technology nodes like 16nm/14nm
• Should be familiar with low-power design and their impact on Back end flow

Experience: 3-12 years
Job Description:
• Should have good timing concepts and able to close timing of Block/SoC independently
• Should have hands on experience in constraint generation
• Hands on experience in Logical synthesis like Design compiler/ Rc compiler
• Knowledge in Formal Verification. Comfortable with LEC/formality tools
• Should able to generate and implement functional Ecos
• Should have experience in Pre-layout and Post layout timing analysis in tools
• Should have experience in two industry standard tools like Primetime/ETS
• Hands on experience in crosstalk timing closure.
• Knowledge in Path based analysis, AOCV, DMSA is a plus.
• Knowledge in complete physical Design flow is a plus.

Experience: 6-10 years
Job Description:
• Expertise in FPGA/SOPC Implementations
• End-to-End FPGA/System Development
• Expertise in Xilinx/Altera FPGA Implementation flow
• Logic Estimation
• FPGA Selection

Experience: 4-9 years
Job Description:
• Strong SOC RTL porting experience for Emulation device , specifically Synopsys Zebu platform
• Experience in Verification Testbench setup and execution using VCS
• Transactor integration experience in Emulation platform
• Experience with LPDDR1/2, PCIe, UART/I2C, JTAG, Lauterbach
• Good debug skills